The present invention is generally directed to electronic circuits and methods, more specifically, to a high-speed current-mirror circuitry and method of operating the same.
Current-mirror circuits are one of the basic building blocks of integrated circuits. Broadly, a current-mirror circuit is operable to reproduce, or mirror, a reference (or drive) current at one location in the circuit at another location within the circuit.
Ideally, the current mirror circuit would be operable to mirror a reference current directly, as mirrored currents should be independent of a load at the mirror points and any given supply voltage. Conventionally, ideal conditions do not exist, and it is only possible to get very close to these objectives.
For purposes of illustration, FIG. 1 is introduced to illustrate a PRIOR ART high-speed current-mirror circuit (generally designated 100). PRIOR ART current-mirror circuit 100 includes two N-channel transistors, namely a N-channel drive transistor 105a and a N-channel mirror transistor 105b. Drive transistor 105a has source 110a coupled to ground, and drain 115a and gate 120a each coupled to each other and to current source 130. Mirror transistor 105b has source 110b coupled to ground, drain 115b coupled to a positive power supply, VDD, via impedance load 135, and gate 120b coupled to drain 115a and gate 120a of drive transistor 105a. 
Current source 130 is illustrated as a generic device comprising a DC current source 131, which produces a DC bias current, I, and an AC signal source 132, which produces an AC signal current, i(ac). The combined output current of current source 130, I+i(ac), flows through drive transistor 105a. 
Drive transistor 105a is in a diode-connected configuration and provides the biasing for mirror transistor 105b. Because is mirror transistor 105b has the same gate-to-source voltage as drive transistor 105a, the drain current in mirror transistor 105b (i.e., the mirror current, I(m)) is give by N[I+i(ac)], where N is a scale factor determined by the relative sizes of drive transistor 105a and mirror transistor 105b. If drive transistor 105a and mirror transistor 105b are identical devices, then N=1, and the mirror current in mirror transistor 105b is the same as the drive current in drive transistor 105a, so that I(m)=I+i(ac).
Drive transistor 105a drives its own gate capacitance because drain 115a is coupled to gate 120a, as well as mirror transistor 105b, effectively driving two gate capacitances. The maximum operating frequency (xe2x80x9cf(max1)xe2x80x9d) of drive transistor 105a is defined as the transconductance of drive transistor 105a (xe2x80x9cGmxe2x80x9d) divided by its total gate and drain capacitances.
For drive transistor 105a, the total capacitance, C(total1), is given by:
C(total1)=Cgs+Cgb+Cgd+Cjd+Cdb.
Note that Cgd is 0, because the gate and drain are shorted.
For mirror transistor 105b, the total capacitance, C(total2), is given by:
C(total2)=Cgs+Cgb+Cgd.
Drive transistor 105a sees the following load:
C(total1)+C(total2),
and the maximum frequency, f(max2), is given by:
Gm/[C(total1)+C(total2)].
However, since the gate-to-source capacitance of the device is the dominant capacitance when it is operating in saturation region, the maximum frequency can be approximated to Gm of the device divided by the gate-to-source capacitance of the device.
Thus, generally speaking, the maximum operating frequency achievable by PRIOR ART current-mirror circuit 100 is the Gm of drive transistor 105a divided by the two gate capacitances, reducing the maximum operating frequency to f(max1)/2 (e.g., for a 10 GHz application, PRIOR ART current-mirror circuit 100 may operate at approximately 5 GHz).
Conventional methods for mirroring current in high frequency applications often suffer because the drive transistor drives two gate-capacitances thereby limiting the maximum frequency operation to f(max2)=f(max1)/2. There is a need in the art for improved high-speed current-mirror circuitry that operates well in current and next-generation applications that require high frequency operations close to f(max1).
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide high-speed current-mirror circuitry and a method of operating the same. According to one exemplary embodiment, an impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a in gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.
According to another exemplary embodiment, an impedance-peaking current mirror comprises a P-channel drive transistor and a P-channel mirror transistor. The P-channel drive transistor has a source coupled to a positive power supply, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The P-channel mirror transistor has a source coupled to the positive power supply, a gate coupled to the drain of the P-channel drive transistor, and a drain coupled to ground via an impedance load.
An important aspect of both embodiments occurs when the impedance-peaking current mirror operates at a sufficiently high frequency to increase the impedance of the inductor such that the inductor isolates the gate to source capacitance of the drive transistor from the gate to source capacitance of the mirror transistor at relatively high frequencies. At high frequencies, a voltage boost is accordingly provided to the mirror transistor to thereby enable operation at frequencies greater than f(max1)/2.
The exemplary inductor may suitably be an on-chip low-Q inductor and the exemplary resistor may suitably be a MOS, polysilcon, or like resistor. The series connection of the inductor and the resistor of the current-mirror circuits provide frequency operation of greater than f(max1)/2, while advantageously preserving the advantages of conventional current-mirror circuits, such as was illustrated with reference to FIG. 1.
Stated differently, the illustrated embodiment cooperatively uses the inductor and the resistor to provide impedance peaking at bandwidths greater than f(max1)/2 as well as damping control. The inductor operates to tune out and isolate the gate capacitances associated with the current mirror and, the resistor operates to further isolate the gate capacitances and control the damping of the LC tank circuit.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; and the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.